The conventional approach to electronic packaging and interconnect has been to package individual integrated circuit (IC) chips in a single package and to attach these packages to a printed circuit board to provide interconnect between the individual IC chips. In recent years, this approach has met with problems of speed, size, and interconnect density due to ever constant demands for reduced size and increased performance from such integrated circuit packages.
Process speed is limited by the fact that individual packages have loading capacitance and inductance associated with their relatively long pins and by the large size of conductor runs in the packages relative to the size of the conductors of a bare IC chip. As the speed of computers and other devices continues to increase, the problem of providing electronic packaging and interconnect which provides maximum performance has become a significant challenge.
Size constraints are particularly prevalent in applications such as portable computers and other handheld electronic devices such as pagers and cellular phones. In these applications, more functionality is continually desired, but the form factor is limited. Thus, the general trend is towards overall decreased weight and size with ever increasing functionality. The problem is to produce electronic packaging and interconnect, which provides such high functionality, but requires minimum space.
Interconnect density is also increasing. As computer manufacturers attempt to increase performance, there is a trend towards wider data and address busses. This allows more data to be communicated in a given clock cycle. As a result, the number of pins on a computer chip is steadily growing. Conventional single chip packaging is being stretched to accommodate the growth in pin count and printed circuit boards are resorting to more layers and finer trace widths to provide interconnect between packages. The problem is that this is raising the cost and complexity of the individual packages, the printed circuit boards which provide the interconnect, and the methods of interconnection from the packages to the printed circuit boards.
One solution to many of the above problems is the MultiChip Module (MCM). In an MCM, bare (unpackaged) IC chips are interconnected by means of a miniature printed circuit board whose interconnect pitch may match the pitch on the IC chip themselves. There are presently two main classes of MCM. These are the chips last MCM and the chips first MCM. In the chips last MCM, the miniature circuit board is fabricated first and then the bare IC chips are attached and interconnected to the circuit board. The method of interconnect is usually wire bond or solder bump. In the chips first MCM, the chips are placed first relative to each other and a miniature circuit board is then built above the chips. The interconnect is formed to the IC chips as an integral part of the processing of the circuit board.
Structures in accordance with the present invention fall into the category of chips first MCMs. In the interest of brevity, only the relevant chips first art is discussed below and, where generic problems of MCMs are pertinent, they are also discussed.
One of the major problems facing the MCM industry is the problem of assuring that the chips which are used in an MCM are 100 percent good. Presently, chips are tested at the bare chip level only to the extent necessary to assure that the chips will probably be good if packaged. Typical yields experienced in the industry are 80 to 97 percent from receipt of the bare chip to complete test and burn-in of the packaged part. Since the yields are multiplicative, the yield of a finished 10 chip MCM using such bare chips will run from 10 to 74 percent. This is obviously not a sufficient yield for a viable MCM business. Thus, some chip vendors are beginning to supply bare chips in fully tested and even burned-in form. These so called "Known Good Die" are supplied at a cost which runs from 3.times. the packaged part cost to as low as 1.times. the packaged part cost. Even at 1.times. packaged part cost, however, this doesn't present a viable business scenario because much of the contributed value of the MCM vendor is the packaging of the bare IC chip. A desirable objective is thus to provide a method and structure whereby chips can be tested and burned-in economically before being committed to the MCM. The subject invention addresses this object.
A further problem in chip testing exists in that multiple chips must work together for the system to function properly. In order to accommodate this fact individual chips are "guard-banded" so that the worst case of all chips in a system can be combined and still work together. This leads to discarding a percentage of chips which typically would have worked in the system, but under worst case combinations would fail. The subject invention solves this problem as well. An additional issue is to test chips as combined chip sets before final incorporation into an MCM. The subject invention also addresses this issue. Even with very complex testing systems, the interaction of complex chips may not be completely simulated by the tester, thereby resulting in undesirable surprises when chips are combined in a system.
Repair of finished MCMs is another major issue which faces the MCM industry. In the chips last approach, the methods of repair differ based upon the original method of interconnect of the chip to the circuit board. In the case of wire bonding, all the wire bonds are broken and the bad chip is removed. A new chip is then placed at the old site and new wire bonds are formed at previously unused sites. This leads to the requirement that additional bonding sites be provided for all chips, whether these sites are ultimately used or not. In addition, there is a significant risk of damage to the circuit board during chip and wire bond removal operations which would necessitate scrapping the entire module. Risk of damage is also a problem with solder bump approaches. With solder bumps, careful burnishing preparation of the solder bump sites must be accomplished to assure that the next chip will make proper connection to the circuit board. In the chips last approach, if the interconnecting circuit board is defective there is no repair procedure possible once the board is populated with chips, necessitating scrapping of the module.
In many low cost approaches no method of repair is provided. This constrains these approaches to those systems where the cost of chips is sufficiently low or the value of the form factor sufficiently high that the penalty of scrapping modules can be withstood. Two significant prior art approaches take this route. The first is the so called "chip on board" approach wherein: the circuit board is formed by conventional laminated printed circuit methods; chips are placed on the board; and then wire bonded to the board and covered with an encapsulant for protection. The second is the so called "Plastic Encapsulated MCM". This approach is a chips first approach wherein chips are encapsulated on one side by plastic encapsulant and the circuit board is built above the chips on the other side. With the plastic encapsulant surrounding the chips there is no way to remove them for repair. This fact is discussed in an article by Fillion and Daum entitled: "CAD/CIM Requirements In Support of Plastic Encapsulated MCM Technology For High Volume Low Cost Electronics," Advancing Microelectronics (September/October 1994). The subject invention is also a chips first technique, but is distinguishable in several ways from the conventional art, one of which is the ability to repair the resultant module.
Two major approaches to chips first are the Advanced Multi-Chip Module (AMCM) approach, and the High Density Interconnect (HDI) approach, along with its offshoots including the Plastic Encapsulated MCM.
A representative cross-section of an AMCM structure, generally denoted 10, is shown in FIG. 1. In the AMCM approach, chips 12 are ground to a precise thickness and accurately placed on a flat substrate 14. Encapsulant 16 is dispensed over the chips 12 and in the area between chips, after which the encapsulant is planarized above the chips. The combination of a controlled chip thickness and accurate planarization of encapsulant above the chips leads to a relatively controlled layer of polymer above the tops of the chips. Via holes are formed in the encapsulant above the pads of the IC chips using an excimer laser. Chip interconnect metallization 18 is sputtered on the surface of encapsulant 16 and in the via holes. The metallization is subsequently built up electrolytically and patterned by photolithographic means. Additional interconnection layers 20 are then built up as required by depositing dielectric, forming via holes, metallizing and patterning.
Several problems exist with structure 10 of FIG. 1. First, the thickness of the chips and of the substrate must be accurately controlled in order to control the thickness of the dielectric above the chips. This is a relatively time consuming and expensive process. Second, the encapsulant surrounds the chips both on the sides and above the chips. The desirable characteristics of the encapsulant above the chips, i.e., as a dielectric, and on the sides of the chips, where used primarily as mechanical support, are conflicting. This necessitates a compromise in properties-where the dielectric properties are not optimum from an electrical view and the mechanical properties are not optimum from a structural view. The subject invention addresses this disadvantage of the AMCM approach by providing a structure wherein the mechanical support portion between chips and dielectric portion above the chips can be wholly different materials.
A representative cross-section of an HDI structure, denoted 30, is shown in FIG. 2. In the HDI approach, instead of thinning chips to a predetermined thickness the substrate 32 is machined with wells 34 of different depths. When the chips 36 are placed in the substrate wells, the tops of the chips are disposed even with the top surface of the substrate. An adhesive is applied to the tops of the chips and a pre-processed layer of polymer film 38 is laminated above the chips 36. Via holes are formed in this overlay layer 38 above the pads 39 of the IC chips 36. Metallization 40 is sputtered on the surface of the overlay layer 38 and in the via holes. The metallization is subsequently built up electrolytically and patterned by photolithographic means. Additional interconnection layers 42 are built up as required by depositing dielectric using coating or laminating means, forming via holes, then metallizing and patterning.
One advantage of structure 30 over the AMCM structure 10 of FIG. 1 is that the thickness of the first layer is only dependent on the thickness of the adhesive and the preformed polymer layer 38. It does not require maintaining tight tolerances on the thickness of the chips or flatness of the substrate. Several problems, however, exist with structure 30. First, machining the substrate to fine tolerances is time consuming and expensive. Second, the overlay layer is unsupported in the well space between chips. Where unsupported, the overlay layer sags and makes lithography difficult. Also, because the chips are in wells, there is no support for pads of an input/output (I/O) layer in the area between chips sharing a common well. These drawbacks can be accommodated somewhat by the use of individual wells for chips, but this is at the expense of increasing package size. The subject invention is a chips first approach that avoids the above-outlined disadvantages of the HDI approach.
In an effort to make a lower cost system, a "Plastic Encapsulated MCM" structure 50, such as depicted in FIG. 3, has been proposed. In this approach, which comprises a variation on the basic HDI approach, the machined substrate is replaced by a plastic encapsulation 52. The basic structure 50 is fabricated by a different set of steps than the HDI approach. Specifically, during fabrication the chips 54 are placed down onto an adhesively coated polymer film that is held to a flat platen. The plastic encapsulation 52 is then formed about the chips. As shown, this plastic encapsulation forms the substrate that protects and supports the chips. Thereafter the structure is removed from the platen and the conventional HDI interconnect structure 56 is formed. Again, a first layer applied above the chips comprises a pre-processed film 58 which is adhesively cured to the IC chips. Unfortunately, there are several identifiable problems with the resultant structure.
First, the structure cannot be repaired, which can be a significant consideration in many applications. In addition, the structure is not inherently thermally efficient because plastic encapsulant is a poor thermal conductor. To combat this, the incorporation of thermal "slugs" beneath chips has been proposed. This, however, adds to process cost and complexity. Further, in applications where space is at a premium the plastic encapsulant adds an undesired thickness to the structure. The subject invention overcomes these drawbacks with a simple structure which maintains the advantages of both the HDI and the AMCM approaches.
Another object achieved by the methods of the subject invention relates to the formation of all layers using photo-imageable polymers. It is desirable to use photo-imageable polymers for the dielectric layers because via holes can be formed therein by simple lithography rather than the more complex methods of laser ablation or plasma etching. In the HDI approach, a preformed film is adhesively bonded over the tops of the chips. In the Plastic Encapsulated MCM technique, the chips are first placed face down on an adhesive coated, preformed film which is attached to a platen. The encapsulant is dispensed and cured, and the structure is removed from the platen for subsequent processing. In both cases the result is the same: there is a preformed film adhesively bonded to the IC chips. The only method of forming vias in a preformed film employs etching means such as laser ablation or plasma etching, either of which may cost three times the process cost associated with photo-patterning. Note that present technology does not provide for a preformed film which could be adhesively bonded to IC chips and which is photo-patternable. Essentially, photo-patternable films must be formed in situ above the integrated circuit chips.
In the AMCM approach, a structural dielectric is employed between and above the integrated circuit chips as shown in FIG. 1. The requirement of a structural dielectric to surround the chips negates the use of a photo-patternable dielectric since photo-imageable dielectrics are solvent born. More particularly, once the photo-patternable material is in place between the chips, it would be difficult to remove the solvent and, even if possible, a high degree of shrinkage would accompany the process such that the resultant structure would in all likelihood be non-planar. Further, it would be difficult to employ a photo-patternable dielectric in the thickness required to implement an AMCM. Finally, with an AMCM structure, it is desirable to cure the encapsulant fully and planarize before forming the interconnect wiring above the encapsulant but if a photo-dielectric is fully cured, then the material is no longer photo-patternable.
The following example is provided for appreciating the higher cost and process complexity required to form via openings in the encapsulant of the AMCM approach. This process comprises sputtering a mask of copper above the encapsulant, applying photoresist to the mask, exposing and developing the photoresist, etching the mask using the photoresist pattern, stripping the photoresist, building the mask electrolytically by electroplating, laser scanning to ablate polymer exposed by the mask, and then removing the mask. Actual costs associated with this approach may be three times or more the costs associated with using a photo-patternable material. Further, processing time required to complete the above-outlined via formation may be on the order of seven hours, while a photo-dielectric material can be applied, exposed and developed in approximately one hour of processing time.
For all of the above reasons, present technology does not allow for the use of a photo-patternable dielectric as the first level dielectric with either the AMCM approach or the HDI approach, including the offshoots thereof.
The preformed film of the HDI approach presents another disadvantage in structures where a portion of the chip is very sensitive to being coated with a dielectric, such as coils on high frequency RF devices. The only way to remove the dielectric from the sensitive area is by aggressive means, such as laser ablation or other etching means which tend to damage the sensitive chip area. Photo-imageable materials, on the other hand, can be removed with a non-aggressive development step, thus leaving sensitive areas intact.
While the subject invention is applicable to multichip modules, it is also applicable to fabrication of low cost, high performance single chip packaging. The basic problem in single chip packaging is to provide connection from the pads of the chip to the pads of the circuit board in the most cost effective and reliable manner while still providing the electrical and thermal performance necessary. With existing single chip structures, chip pads are connected by solder balls to small circuit boards which contain solder bumps on the opposite side. This process has two drawbacks; first it requires the use of chips which have solder balls and second it often requires the use of an underfill polymer to take up the expansion difference between the circuit board and the chip. Without the underfill, the solder balls are stressed beyond their elastic limit and fail prematurely during thermal cycling. In a second "chip scale" packaging approach, a wafer is covered with a relatively thick "buffer" layer of polymer, vias are formed and patterned metal makes contact to the chip pads. Solder bumps are then formed on top of the chips. In this structure the solder bump array is necessarily restricted to the size of the chip. If, for example, the chip undergoes a design rule shrink, the package must change accordingly. The subject invention avoids this drawback of the prior art.